As semiconductor devices are scaled-down, the size of conductive structures and intervals between the structures may also be scaled down. However, a reduction of the size and/or intervals between the structures may increase electrical resistance in the structures, and as such, may deteriorate the electrical reliability of a semiconductor device.
Accordingly, stacked semiconductor devices have been implemented in which the conductive structures may be vertically stacked on a substrate, as disclosed in U.S. Pat. No. 6,538,330. The stacked structure may be widely applied to various devices, such as static random access memory (SRAM) devices and/or system on chip (SOC) devices.
In particular, because an SRAM device generally includes six transistors in a unit cell, a multilayer structure in which the six transistors are vertically stacked may be employed as a unit structure of the transistor. For example, when the six transistors of the SRAM device are stacked in a double layer structure (i.e., a double stacked SRAM device), NMOS (N-channel Metal Oxide Semiconductor) transistors corresponding to a pair of pull down devices and a pair of access devices may be formed at a lower portion of the SRAM device. PMOS (P-channel Metal Oxide Semiconductor) transistors corresponding to a pair of pull up devices may be formed at an upper portion of the SRAM device, and may be electrically connected with the NMOS transistors. As another example, when the six transistors of the SRAM device are stacked in a triple layer structure (known as a triple-stacked SRAM device), first NMOS transistors corresponding to a pair of pull down devices may be formed at a lower portion of the SRAM device. PMOS transistors corresponding to a pair of pull up devices may be formed at an upper portion of the first NMOS transistors, and may be electrically connected with the first NMOS transistors. Second NMOS transistors corresponding to a pair of access devices may be formed at an upper portion of the PMOS transistors.
In such a stacked semiconductor device, conductive structures such as transistors may be vertically stacked in a multilayer structure. As such, insulation interlayer patterns in the multilayer structure may be formed on single crystalline channel layers.
In general, operational characteristics of NMOS transistors may be superior when the channel layer includes single crystalline silicon, while operational characteristics of PMOS transistors may be superior when the channel layer includes single crystalline germanium. The single crystalline silicon channel layer may be formed by a heat treatment. A non-crystalline silicon thin layer, such as an amorphous silicon layer, may be formed on a substrate, and a heat treatment (such as laser irradiation) may be performed on the non-crystalline silicon thin layer. As a result, non-crystalline silicon may be transformed into crystalline silicon, thereby forming the single crystalline silicon layer. In contrast, the single crystalline germanium channel layer may be formed by a zone melting re-crystallization (ZMR) process. Examples of ZMR processes are disclosed in U.S. Pat. Nos. 6,121,112 and 6,885,031. In particular, a ZMR process for forming the single crystalline germanium channel layer may employ a heat treatment performed at a temperature higher than about 1,400° C. for a relatively long period of time.
Severe thermal stress may not result from the heat treatment used to form the single crystalline silicon channel layer, because the heat treatment may be performed at a relatively low temperature. As such, operational characteristics of semiconductor devices may not be deteriorated due to this heat treatment. In contrast, thermal stress may be applied to a unit structure underlying the channel layer during the high-temperature heat treatment used to form the single crystalline germanium channel layer, which may thereby deteriorate operational characteristics of the semiconductor device.
Accordingly, single crystalline silicon is typically used as the channel layer in conventional stacked semiconductor devices, regardless of transistor type (NMOS or PMOS). As such, operational characteristics of PMOS transistors may not be optimized, which may negatively affect the performance of semiconductor devices.